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MJB41C (NPN), MJB42C (PNP)
Preferred Devices
Complementary Silicon Plastic Power Transistors
D2PAK for Surface Mount
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* Lead Formed for Surface Mount Applications in Plastic Sleeves * *
(No Suffix) Lead Formed Version in 16 mm Tape & Reel ("T4" Suffix) Electrically the Same as TIP41 and T1P42 Series
MAXIMUM RATINGS
Rating Collector-Emitter Voltage Collector-Base Voltage Emitter-Base Voltage Symbol VCEO VCB VEB IC IB Value 100 100 5.0 6.0 10 Unit Vdc Vdc Vdc Adc Adc
COMPLEMENTARY SILICON POWER TRANSISTORS 6 AMPERES 100 VOLTS 65 WATTS
III I I I I IIIIIIIIIIIIIIIII II III I IIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIII III I I II I I IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII II I III I I I IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII II
Collector Current - Continuous - Peak Base Current 2.0 Total Power Dissipation @ TC = 25_C Derate above 25_C Total Power Dissipation @ TA = 25_C Derate above 25_C PD 65 0.52 Watts W/_C Watts W/_C mJ _C PD 2.0 0.016 62.5 Unclamped Inductive Load Energy (Note 1.) Operating and Storage Junction Temperature Range E TJ, Tstg -65 to +150
MARKING DIAGRAM
MJB4xC YWW D2PAK CASE 418B STYLE 1 MJB4xC = Specific Device Code x = 1 or 2 Y = Year WW = Work Week
ORDERING INFORMATION
Device MJB41C MJB41CT4 MJB42C MJB42CT4 Package D2PAK D2PAK D2PAK D2PAK Shipping 50 Units/Rail 800/Tape & Reel 50 Units/Rail 800/Tape & Reel
THERMAL CHARACTERISTICS
Characteristic
Symbol RJC RJA RJA TL
Max
Unit
Thermal Resistance, Junction to Case
1.92 62.5 50
_C/W _C/W _C/W _C
Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8 from Case for 10 Seconds
260
Preferred devices are recommended choices for future use and best overall value.
1. IC = 2.5 A, L = 20 mH, P.R.F. = 10 Hz, VCC = 10 V, RBE = 100 W 2. When surface mounted to an FR-4 board using the minimum recommended pad size.
(c) Semiconductor Components Industries, LLC, 2001
1
March, 2001 - Rev. 0
Publication Order Number: MJB41C/D
MJB41C (NPN), MJB42C (PNP)
PD, POWER DISSIPATION (WATTS)
t, TIME ( s)
II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Symbol Min Max Unit Collector-Emitter Sustaining Voltage (Note 3.) (IC = 30 mAdc, IB = 0) Collector Cutoff Current (VCE = 60 Vdc, IB = 0) Emitter Cutoff Current (VBE = 5.0 Vdc, IC = 0) Collector Cutoff Current (VCE = 100 Vdc, VEB = 0) VCEO(sus) ICEO ICES IEBO hFE 100 - - - - Vdc 0.7 50 mAdc Adc mAdc - 100 ON CHARACTERISTICS (Note 3.) DC Current Gain (IC = 0.3 Adc, VCE = 4.0 Vdc) DC Current Gain (IC = 3.0 Adc, VCE = 4.0 Vdc) 30 15 - - - 75 Collector-Emitter Saturation Voltage (IC = 6.0 Adc, IB = 600 mAdc) Base-Emitter On Voltage (IC = 6.0 Adc, VCE = 4.0 Vdc) Current-Gain - Bandwidth Product (IC = 500 mAdc, VCE = 10 Vdc, ftest = 1.0 MHz) Small-Signal Current Gain (IC = 0.5 Adc, VCE = 10 Vdc, f = 1.0 kHz) VCE(sat) VBE(on) fT 1.5 2.0 Vdc Vdc DYNAMIC CHARACTERISTICS 3.0 20 - - MHz - hfe 3. Pulse Test: Pulse Width v 300 s, Duty Cycle v 2.0%. TA 4.0 TC 80 3.0 60 TC 2.0 40 TA 1.0 20 0 0 0 20 40 60 100 80 T, TEMPERATURE (C) 120 140 160
Figure 1. Power Derating
VCC +30 V 25 s +11 V 0 -9.0 V tr, tf 10 ns DUTY CYCLE = 1.0% RB D1 -4 V RC 2.0 1.0 SCOPE 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.06 tr TJ = 25C VCC = 30 V IC/IB = 10
td @ VBE(off) 5.0 V
RB and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS D1 MUST BE FAST RECOVERY TYPE, e.g.: 1N5825 USED ABOVE IB 100 mA MSD6100 USED BELOW IB 100 mA
0.1
0.4 0.6 0.2 2.0 1.0 IC, COLLECTOR CURRENT (AMP)
4.0
6.0
Figure 2. Switching Time Test Circuit
Figure 3. Turn-On Time
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MJB41C (NPN), MJB42C (PNP)
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.03 0.02 0.01 0.01
D = 0.5 0.2 0.1 0.05 0.02 0.01 0.02 ZJC(t) = r(t) RJC RJC = 1.92C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) ZJC(t) 0.2 0.5 1.0 2.0 5.0 t, TIME (ms) 10 20 50 P(pk)
t1
t2
SINGLE PULSE 0.05 1.0
DUTY CYCLE, D = t1/t2 100 200 500 1.0 k
Figure 4. Thermal Response
10 IC, COLLECTOR CURRENT (AMP) 5.0 3.0 2.0 1.0 0.5 0.3 0.2 1.0 ms SECONDARY BREAKDOWN LTD BONDING WIRE LTD THERMAL LIMITATION @ TC = 25C (SINGLE PULSE) CURVES APPLY BELOW RATED VCEO 0.5 ms
5.0 ms
0.1 5.0
40 10 20 60 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
80 100
There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC - VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 5 is based on TJ(pk) = 150_C; TC is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided TJ(pk) v 150_C. TJ(pk) may be calculated from the data in Figure 4. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown.
Figure 5. Active-Region Safe Operating Area
5.0 3.0 2.0 1.0 0.7 0.5 0.3 0.2 0.1 0.07 0.05 0.06 tf ts TJ = 25C VCC = 30 V IC/IB = 10 IB1 = IB2 300 200 C, CAPACITANCE (pF) Cib 100 70 50 30 0.5 Cob TJ = 25C
t, TIME ( s)
0.1
0.2 0.4 0.6 1.0 2.0 IC, COLLECTOR CURRENT (AMP)
4.0
6.0
1.0
2.0 3.0 5.0 10 20 VR, REVERSE VOLTAGE (VOLTS)
30
50
Figure 6. Turn-Off Time
Figure 7. Capacitance
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MJB41C (NPN), MJB42C (PNP)
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) 500 300 200 100 70 50 30 20 10 7.0 5.0 0.06 VCE = 2.0 V TJ = 150C 25C 2.0 TJ = 25C 1.6 1.2 0.8 0.4 0 IC = 1.0 A 2.5 A 5.0 A
hFE, DC CURRENT GAIN
-55C
0.1
0.2 0.3 0.4 0.6 1.0 2.0 IC, COLLECTOR CURRENT (AMP)
4.0
6.0
10
20
30
50 100 200 300 IB, BASE CURRENT (mA)
500
1000
Figure 8. DC Current Gain
Figure 9. Collector Saturation Region
V, TEMPERATURE COEFFICIENTS (mV/C)
2.0 TJ = 25C 1.6 V, VOLTAGE (VOLTS) 1.2 0.8 0.4 0 0.06 VBE(sat) @ IC/IB = 10 VBE @ VCE = 4.0 V VCE(sat) @ IC/IB = 10 0.1 0.2 0.3 0.4 0.6 1.0 2.0 3.0 4.0 6.0
+2.5 +2.0 +1.5 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 0.06 0.1 0.2 0.3 0.5 VB FOR VBE *VC FOR VCE(sat) +25C to +150C -55C to +25C +25C to +150C *APPLIES FOR IC/IB hFE/4
-55C to +25C 1.0 2.0 3.0 4.0 6.0
IC, COLLECTOR CURRENT (AMP)
IC, COLLECTOR CURRENT (AMP)
Figure 10. "On" Voltages
R BE , EXTERNAL BASE-EMITTER RESISTANCE (OHMS)
Figure 11. Temperature Coefficients
103 IC, COLLECTOR CURRENT ( A) 102 101 100 10-1 10-2 REVERSE IC = ICES FORWARD VCE = 30 V TJ = 150C
10 M VCE = 30 V IC = 10 x ICES IC ICES
1.0 M 100 k 10 k 1.0 k 0.1 k
100C 25C
IC = 2 x ICES (TYPICAL ICES VALUES OBTAINED FROM FIGURE 12) 20 40 60 80 100 120 140 160
10-3 -0.3 -0.2
-0.1
0
+0.1 +0.2 +0.3
+0.4 +0.5 +0.6
+0.7
VBE, BASE-EMITTER VOLTAGE (VOLTS)
TJ, JUNCTION TEMPERATURE (C)
Figure 12. Collector Cut-Off Region
Figure 13. Effects of Base-Emitter Resistance
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MJB41C (NPN), MJB42C (PNP) INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection
0.33 8.38
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
0.42 10.66
0.08 2.032 0.04 1.016 0.12 3.05 0.63 17.02
0.24 6.096
inches mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE The power dissipation for a surface mount device is a function of the Collector pad size. These can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet, PD can be calculated as follows:
PD = TJ(max) - TA RJA
Although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. For example, a graph of RJA versus Collector pad area is shown in Figure 14.
R JA , Thermal Resistance, Junctionto Ambient ( C/W) 70 60 50 40 30 20 3.5 Watts 5 Watts Board Material = 0.0625 G-10/FR-4, 2 oz Copper 2.5 Watts TA = 25C
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device. For a D2PAK device, PD is calculated as follows.
PD = 150C - 25C = 2.5 Watts 50C/W
0
2
4
6 8 10 A, Area (square inches)
12
14
16
The 50C/W for the D2PAK package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts. There are other alternatives to achieving higher power dissipation from the surface mount packages. One is to increase the area of the Collector pad. By increasing the area of the collection pad, the power dissipation can be increased.
Figure 14. Thermal Resistance versus Collector Pad Area for the D2PAK Package (Typical)
Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad(R). Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint.
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MJB41C (NPN), MJB42C (PNP)
SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC-59, SC-70/SOT-323, SOD-123, SOT-23, SOT-143, SOT-223, SO-8, SO-14, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the Collector pad, misalignment and/or "tombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 15. shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the Collector pad is not critical as long as it allows approximately 50% of the pad to be covered with paste.
Figure 15. Typical Stencil for DPAK and D2PAK Packages
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering.
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CCC CCCCC C C CC CCCCC C CC CCCCC CCC
CC CC CC CC CC
SOLDER PASTE OPENINGS
STENCIL
MJB41C (NPN), MJB42C (PNP)
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16. shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 6 VENT STEP 7 COOLING 205 TO 219C PEAK AT SOLDER JOINT
STEP 1 PREHEAT ZONE 1 RAMP" 200C
STEP 2 STEP 3 VENT HEATING SOAK" ZONES 2 & 5 RAMP"
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 SPIKE" SOAK" 170C 160C
150C
100C 100C
140C
SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
50C
DESIRED CURVE FOR LOW MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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MJB41C (NPN), MJB42C (PNP)
PACKAGE DIMENSIONS D2PAK CASE 418B-03 ISSUE D
C E -B-
4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E G H J K S V INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 BASE COLLECTOR EMITTER COLLECTOR MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40
V
A
1 2 3
S
-T-
SEATING PLANE
K G D H
3 PL M
J
0.13 (0.005)
TB
M
STYLE 1: PIN 1. 2. 3. 4.
Thermal Clad is a registered trademark of the Bergquist Company
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